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NAS200.Hardware History

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January 27, 2008, at 03:50 PM by Jac Goudsmit -- Fix bad link
Changed line 17 from:

According to the OpenWRT website, the R3210-G is functionally equivalent to the R8610-G but "32" represents the commercial version whereas "86" represents the industrial version. Full datasheet of the R8610-G here: http://wiki.openwrt.org/RDCPort?action=AttachFile&do=get&target=R8610-G_D01_20051207.pdf (on the OpenWRT? website where someone is working on a port for the R8610).

to:

According to the RDC page on the OpenWRT website, the R3210-G is functionally equivalent to the R8610-G but "32" represents the commercial version whereas "86" represents the industrial version. Full datasheet of the R8610-G here: http://wiki.openwrt.org/RDCPort?action=AttachFile&do=get&target=R8610-G_D01_20051207.pdf (on the OpenWRT) website where someone is working on a port for the R8610).

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January 27, 2008, at 03:49 PM by Jac Goudsmit -- Add link to R8610 datasheet
Changed lines 15-16 from:

Data sheet here: http://www.rdc.com.tw/Uploads/datasheet/R3210_Mbrief_20061121.pdf.

to:

Data sheet (brief) here: http://www.rdc.com.tw/Uploads/datasheet/R3210_Mbrief_20061121.pdf.

According to the OpenWRT website, the R3210-G is functionally equivalent to the R8610-G but "32" represents the commercial version whereas "86" represents the industrial version. Full datasheet of the R8610-G here: http://wiki.openwrt.org/RDCPort?action=AttachFile&do=get&target=R8610-G_D01_20051207.pdf (on the OpenWRT? website where someone is working on a port for the R8610).

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August 22, 2007, at 04:50 PM by fcarolo -- formatting
Changed lines 14-16 from:

The RDC R3210-G CPU is a RISC-based SoC? (system-on-chip) that executes the i486 instruction set. Data sheet here <<http://www.rdc.com.tw/Uploads/datasheet/R3210_Mbrief_20061121.pdf>>

to:

The RDC R3210-G CPU is a RISC-based SoC (system-on-chip) that executes the i486 instruction set. Data sheet here: http://www.rdc.com.tw/Uploads/datasheet/R3210_Mbrief_20061121.pdf.

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August 21, 2007, at 03:12 AM by mrkzander --
Changed lines 9-16 from:

Serial Console Port at JP1

to:

Serial Console Port at JP1

CPU Info

The RDC R3210-G CPU is a RISC-based SoC? (system-on-chip) that executes the i486 instruction set. Data sheet here <<http://www.rdc.com.tw/Uploads/datasheet/R3210_Mbrief_20061121.pdf>>

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August 08, 2007, at 02:15 PM by fcarolo -- fixed false wikilink
Changed line 9 from:

Serial Console Port at JP1?

to:

Serial Console Port at JP1

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August 04, 2007, at 01:24 PM by dyoung --
Changed lines 3-8 from:

SATA Controller is Silicon Image SiL3512ECTU128?

RAM is 32MB V54C325616VDI6?

Flash is JS28F640P?

to:

SATA Controller is Silicon Image SiL3512ECTU128

RAM is 32MB V54C325616VDI6

Flash is JS28F640P

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August 04, 2007, at 10:56 AM by dyoung --
Added lines 1-9:

CPU is RDC R3210-G

SATA Controller is Silicon Image SiL3512ECTU128?

RAM is 32MB V54C325616VDI6?

Flash is JS28F640P?

Serial Console Port at JP1?

Restore
view · edit · print · history · Last edited by Jac Goudsmit.
Based on work by Jac Goudsmit, fcarolo, mrkzander, and dyoung.
Originally by dyoung.
Page last modified on January 27, 2008, at 03:50 PM