NSLU2-Linux
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NAS100d.GPIOConnections History

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November 13, 2005, at 05:14 AM by rwhitby --
Changed lines 10-11 from:
GPIO[5]Y25I²C SCLRTC - SCLOutput
GPIO[6]V21I²C SDARTC - SDAInput/Tristate
to:
GPIO[5]Y25I²C SDARTC - SDAInput/Tristate
GPIO[6]V21I²C SCLRTC - SCLOutput
Restore
November 11, 2005, at 02:42 PM by rwhitby --
Changed lines 5-8 from:
GPIO[0]Y22WLAN LED (0 = Green, 1 = Off) Output
GPIO[1]W21  Output
GPIO[2]AC26  Output
GPIO[3]AA24Disk LED (0 = Yellow, 1 = Off)Overrides normal green flashing operationOutput
to:
GPIO[0]Y22WLAN LED (0 = Green, 1 = Off) Input (switch to Output to override)
GPIO[1]W21  Input
GPIO[2]AC26  Input
GPIO[3]AA24Disk LED (0 = Yellow, 1 = Off)Overrides normal green flashing operationInput (switch to Output to override)
Changed lines 10-11 from:
GPIO[5]Y25I²C SDARTC - SDATristate
GPIO[6]V21I²C SCLRTC - SCLOutput
to:
GPIO[5]Y25I²C SCLRTC - SCLOutput
GPIO[6]V21I²C SDARTC - SDAInput/Tristate
Restore
November 11, 2005, at 05:33 AM by rwhitby --
Changed line 17 from:
GPIO[12]W26Power Off (1 = Turn Off) Output
to:
GPIO[12]W26Power Off (1 = Turn Off) Input (switch to Output to use)
Restore
November 11, 2005, at 05:31 AM by rwhitby --
Changed line 15 from:
GPIO[10]Y26PCI INTB (IRQ 27)Slot 2, Pin 1 (MiniPCI?, WLAN)Input
to:
GPIO[10]Y26PCI INTB (IRQ 27)Slot 2, Pin 1 (MiniPCI, WLAN)Input
Restore
November 11, 2005, at 05:31 AM by rwhitby --
Changed lines 15-16 from:
GPIO[10]Y26PCI INTB (IRQ 27)Slot 2, Pin 1Input
GPIO[11]W25PCI INTA (IRQ 28)Slot 1, Pin 1, IDE ControllerInput
to:
GPIO[10]Y26PCI INTB (IRQ 27)Slot 2, Pin 1 (MiniPCI?, WLAN)Input
GPIO[11]W25PCI INTA (IRQ 28)Slot 1, Pin 1, (IDE Controller)Input
Restore
November 11, 2005, at 05:29 AM by rwhitby --
Changed lines 12-14 from:
GPIO[7]AA26PCI INTE (IRQ 24)Slot 3, Pin 3Input
GPIO[8]W23PCI INTD (IRQ 25)Slot 3, Pin 2Input
GPIO[9]V22PCI INTC (IRQ 26)Slot 3, Pin 1Input
to:
GPIO[7]AA26PCI INTE (IRQ 24)Slot 3, Pin 3 (USB EHCI)Input
GPIO[8]W23PCI INTD (IRQ 25)Slot 3, Pin 2 (USB UHCI)Input
GPIO[9]V22PCI INTC (IRQ 26)Slot 3, Pin 1 (USB UHCI)Input
Restore
November 11, 2005, at 05:27 AM by rwhitby --
Changed line 16 from:
GPIO[11]W25PCI INTA (IRQ 28)Slot 1, Pin 1Input
to:
GPIO[11]W25PCI INTA (IRQ 28)Slot 1, Pin 1, IDE ControllerInput
Restore
November 11, 2005, at 05:16 AM by rwhitby --
Changed lines 1-2 from:

The IXP420 CPU has 16 General Purpose Input/Output (GPIO) pins which are used to interface to external hardware. In the case of the NAS100D?, the GPIO pins are used to monitor the buttons, control the LEDs, connect to the RTC, IDE controller and USB 2.0 controller.

to:

The IXP420 CPU has 16 General Purpose Input/Output (GPIO) pins which are used to interface to external hardware. In the case of the NAS100D, the GPIO pins are used to monitor the buttons, control the LEDs, connect to the RTC, IDE controller and USB 2.0 controller.

Changed line 5 from:
GPIO[0]Y22WLAN LED (0 = On, 1 = Off) Output
to:
GPIO[0]Y22WLAN LED (0 = Green, 1 = Off) Output
Changed line 8 from:
GPIO[3]AA24Disk LED (0 = On, 1 = Off) Output
to:
GPIO[3]AA24Disk LED (0 = Yellow, 1 = Off)Overrides normal green flashing operationOutput
Changed lines 20-23 from:
GPIO[15]U25Power LED (0 = On, 1 = Flashing) Output
TBF Expansion Bus Clock (33MHz)IXP420 - EX_CLK - Ball M32Output
TBF PCI Clock (33MHz)TBDOutput
to:
GPIO[15]U25Power LED (0 = Solid Blue, 1 = Flashing Blue) Output
Restore
November 11, 2005, at 04:57 AM by rwhitby --
Changed line 8 from:
GPIO[3]AA24  Output
to:
GPIO[3]AA24Disk LED (0 = On, 1 = Off) Output
Restore
November 11, 2005, at 04:53 AM by rwhitby --
Changed lines 1-2 from:

The IXP420 CPU has 16 General Purpose Input/Output (GPIO) pins which are used to interface to external hardware. In the case of the NSLU2, the GPIO pins are used to monitor the buttons, control the LEDs, connect to the RTC, IDE controller and USB 2.0 controller.

to:

The IXP420 CPU has 16 General Purpose Input/Output (GPIO) pins which are used to interface to external hardware. In the case of the NAS100D?, the GPIO pins are used to monitor the buttons, control the LEDs, connect to the RTC, IDE controller and USB 2.0 controller.

Changed line 5 from:
GPIO[0]Y22WAN LED (0 = On, 1 = Off) Output
to:
GPIO[0]Y22WLAN LED (0 = On, 1 = Off) Output
Restore
November 11, 2005, at 04:52 AM by rwhitby --
Changed line 5 from:
GPIO[0]Y22WAN LED (0 = Lit) Output
to:
GPIO[0]Y22WAN LED (0 = On, 1 = Off) Output
Changed lines 7-8 from:
GPIO[2]AC26TBD Output
GPIO[3]AA24TBD Output
to:
GPIO[2]AC26  Output
GPIO[3]AA24  Output
Changed lines 17-20 from:
GPIO[12]W26Power Off (1 = Turn Off)TBDOutput
GPIO[13]V24PCI ResetTBDOutput
GPIO[14]U22Power Button (1 = Pushed)TBDInput
GPIO[15]U25Expansion Bus Clock (33MHz)IXP420 - EX_CLK - Ball M32Output
to:
GPIO[12]W26Power Off (1 = Turn Off) Output
GPIO[13]V24PCI Reset Output
GPIO[14]U22Power Button (1 = Pushed) Input
GPIO[15]U25Power LED (0 = On, 1 = Flashing) Output
TBF Expansion Bus Clock (33MHz)IXP420 - EX_CLK - Ball M32Output
Restore
November 11, 2005, at 04:48 AM by rwhitby --
Changed lines 12-16 from:
GPIO[7]AA26PCI INTE (IRQ24?)Slot 3, Pin 3Input
GPIO[8]W23PCI INTDSlot 3, Pin 2Input
GPIO[9]V22PCI INTCSlot 3, Pin 1Input
GPIO[10]Y26PCI INTBSlot 2, Pin 1Input
GPIO[11]W25PCI INTASlot 1, Pin 1Input
to:
GPIO[7]AA26PCI INTE (IRQ 24)Slot 3, Pin 3Input
GPIO[8]W23PCI INTD (IRQ 25)Slot 3, Pin 2Input
GPIO[9]V22PCI INTC (IRQ 26)Slot 3, Pin 1Input
GPIO[10]Y26PCI INTB (IRQ 27)Slot 2, Pin 1Input
GPIO[11]W25PCI INTA (IRQ 28)Slot 1, Pin 1Input
Restore
November 11, 2005, at 04:46 AM by rwhitby --
Changed line 12 from:
GPIO[7]AA26PCI INTESlot 3, Pin 3Input
to:
GPIO[7]AA26PCI INTE (IRQ24?)Slot 3, Pin 3Input
Restore
November 11, 2005, at 04:45 AM by rwhitby --
Changed lines 38-39 from:

Location 0xc8004004 (GPOER) is set to 0x00005fdf (0b1001 1111 1101 1111), meaning GPIO[15,12:6,4:0] are inputs or tristated, and GPIO[14:13,5] are outputs.

to:

Location 0xc8004004 (GPOER) is set to 0x00005fdf (0b0101 1111 1101 1111), meaning GPIO[14,12:6,4:0] are inputs or tristated, and GPIO[15,13,5] are outputs.

Restore
November 11, 2005, at 04:37 AM by rwhitby --
Changed lines 32-33 from:
 GPIT1R? = 0x00201248
 GPIT2R? = 0x00000249
to:
 GPIT1R = 0x00201248
 GPIT2R = 0x00000249
Restore
November 11, 2005, at 04:37 AM by rwhitby --
Added lines 25-51:

(From Linux:) 

 # ./gpio 0
 GPOUTR = 0x000020e0
 GPOER  = 0x00005fdf
 GPINR  = 0x00002ffd
 GPISR  = 0x0000a06b
 GPIT1R? = 0x00201248
 GPIT2R? = 0x00000249
 GPCLKR = 0x00000000

Location 0xc8004000 (GPOUTR) is set to 0x000020e0 (0b0010 0000 1110 0000), meaning GPIO[13,7,6,5] are set to 1.

Location 0xc8004004 (GPOER) is set to 0x00005fdf (0b1001 1111 1101 1111), meaning GPIO[15,12:6,4:0] are inputs or tristated, and GPIO[14:13,5] are outputs.

Location 0xc8004008 (GPINR) is set to 0x00002ffd (0b0010 1111 1111 1101), meaning GPIO[15,14,12,1] are reading as 0, and the rest are reading as 1.

Location 0xc800400c (GPISR) is set to 0x0000a06b (0b1010 0000 0101 1011), meaning there are interrupts pending on GPIO[6,4,3,1,0].

Location 0xc8004010 (GPIT1R) is set to 0x00201248 (0b0000 0000 0010 0000 0001 0010 0100 1000), meaning GPIO[6,5,0] are active high interrupts, and GPIO[7,4:1] are active low interrupts.

Location 0xc8004014 (GPIT2R) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.

Location 0xc8004018 (GPCLKR) is set to 0x00000000 (0b0000 0000 0000 0000 0000 0000 0000 0000), meaning GPIO[15:14] are normal outputs.

(From RedBoot:)

Deleted lines 70-91:
  1. ./gpio 0

GPOUTR = 0x000020e0 GPOER = 0x00005fdf GPINR = 0x00002ffd GPISR = 0x0000a06b GPIT1R? = 0x00201248 GPIT2R? = 0x00000249 GPCLKR = 0x00000000

Location 0xc8004000 (GPOUTR) is set to 0x000020e0 (0b0010 0000 1110 0000), meaning GPIO[13,7,6,5] are set to 1.

Location 0xc8004004 (GPOER) is set to 0x00005fdf (0b1001 1111 1101 1111), meaning GPIO[15,12:6,4:0] are inputs or tristated, and GPIO[14:13,5] are outputs.

Location 0xc8004008 (GPINR) is set to 0x00002ffd (0b0010 1111 1111 1101), meaning GPIO[15,14,12,1] are reading as 0, and the rest are reading as 1.

Location 0xc800400c (GPISR) is set to 0x0000a06b (0b1010 0000 0101 1011), meaning there are interrupts pending on GPIO[6,4,3,1,0].

Location 0xc8004010 (GPIT1R) is set to 0x00201248 (0b0000 0000 0010 0000 0001 0010 0100 1000), meaning GPIO[6,5,0] are active high interrupts, and GPIO[7,4:1] are active low interrupts.

Location 0xc8004014 (GPIT2R) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.

Location 0xc8004018 (GPCLKR) is set to 0x00000000 (0b0000 0000 0000 0000 0000 0000 0000 0000), meaning GPIO[15:14] are normal outputs.

Restore
November 11, 2005, at 04:36 AM by rwhitby --
Added lines 43-65:
  1. ./gpio 0

GPOUTR = 0x000020e0 GPOER = 0x00005fdf GPINR = 0x00002ffd GPISR = 0x0000a06b GPIT1R? = 0x00201248 GPIT2R? = 0x00000249 GPCLKR = 0x00000000

Location 0xc8004000 (GPOUTR) is set to 0x000020e0 (0b0010 0000 1110 0000), meaning GPIO[13,7,6,5] are set to 1.

Location 0xc8004004 (GPOER) is set to 0x00005fdf (0b1001 1111 1101 1111), meaning GPIO[15,12:6,4:0] are inputs or tristated, and GPIO[14:13,5] are outputs.

Location 0xc8004008 (GPINR) is set to 0x00002ffd (0b0010 1111 1111 1101), meaning GPIO[15,14,12,1] are reading as 0, and the rest are reading as 1.

Location 0xc800400c (GPISR) is set to 0x0000a06b (0b1010 0000 0101 1011), meaning there are interrupts pending on GPIO[6,4,3,1,0].

Location 0xc8004010 (GPIT1R) is set to 0x00201248 (0b0000 0000 0010 0000 0001 0010 0100 1000), meaning GPIO[6,5,0] are active high interrupts, and GPIO[7,4:1] are active low interrupts.

Location 0xc8004014 (GPIT2R) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.

Location 0xc8004018 (GPCLKR) is set to 0x00000000 (0b0000 0000 0000 0000 0000 0000 0000 0000), meaning GPIO[15:14] are normal outputs.

Restore
November 11, 2005, at 03:56 AM by rwhitby --
Changed line 9 from:
GPIO[4]AB26Reset Button (0 = pushed) Input
to:
GPIO[4]AB26Reset Button (0 = Pushed) Input
Restore
November 11, 2005, at 03:56 AM by rwhitby --
Changed line 5 from:
GPIO[0]Y22Wifi LED Output
to:
GPIO[0]Y22WAN LED (0 = Lit) Output
Changed line 9 from:
GPIO[4]AB26TBD Output
to:
GPIO[4]AB26Reset Button (0 = pushed) Input
Changed line 19 from:
GPIO[14]U22PCI Clock (33MHz)TBDOutput
to:
GPIO[14]U22Power Button (1 = Pushed)TBDInput
Changed lines 21-23 from:
TBF Reset Button (0 = Pressed)Reset ButtonInput
TBF Power Button (Pulse when state change)Power Button via flipflopInput
to:
TBF PCI Clock (33MHz)TBDOutput
Restore
November 11, 2005, at 03:40 AM by rwhitby --
Changed lines 5-6 from:
GPIO[0]Y22TBD Output
GPIO[1]W21TBD Output
to:
GPIO[0]Y22Wifi LED Output
GPIO[1]W21  Output
Restore
November 10, 2005, at 08:28 PM by rwhitby --
Changed lines 12-16 from:
GPIO[7]AA26PCI INTE Input
GPIO[8]W23PCI INTD Input
GPIO[9]V22PCI INTC Input
GPIO[10]Y26PCI INTB Input
GPIO[11]W25PCI INTA Input
to:
GPIO[7]AA26PCI INTESlot 3, Pin 3Input
GPIO[8]W23PCI INTDSlot 3, Pin 2Input
GPIO[9]V22PCI INTCSlot 3, Pin 1Input
GPIO[10]Y26PCI INTBSlot 2, Pin 1Input
GPIO[11]W25PCI INTASlot 1, Pin 1Input
Restore
November 10, 2005, at 08:09 PM by rwhitby --
Changed lines 12-13 from:
GPIO[7]AA26PCI INTA Input
GPIO[8]W23PCI INTB Input
to:
GPIO[7]AA26PCI INTE Input
GPIO[8]W23PCI INTD Input
Changed lines 15-16 from:
GPIO[10]Y26PCI INTD Input
GPIO[11]W25PCI INTE Input
to:
GPIO[10]Y26PCI INTB Input
GPIO[11]W25PCI INTA Input
Restore
November 10, 2005, at 02:49 PM by rwhitby --
Changed lines 5-8 from:
GPIO[0]Y22Red Status LED (1 = On)Status LEDOutput
GPIO[1]W21Green Ready LED (1 = On)Ready LEDOutput
GPIO[2]AC26Disk 2 LED (0 = On)Disk 2 LEDOutput
GPIO[3]AA24Disk 1 LED (0 = On)Disk 1 LEDOutput
to:
GPIO[0]Y22TBD Output
GPIO[1]W21TBD Output
GPIO[2]AC26TBD Output
GPIO[3]AA24TBD Output
Restore
November 10, 2005, at 02:48 PM by rwhitby --
Changed lines 31-38 from:
 Location 0xc8004000 (GPOUTR) is set to 0x000020C0 (0b0010 0000 1100 0000), meaning GPIO[13,7,6] are set to 1.

 Location 0xc8004004 (GPOER) is set to 0x00001F3F (0b0001 1111 0011 1111), meaning GPIO[12:8] and GPIO[5:0] are inputs or tristated, and GPIO[15:13] and GPIO[7:6] are outputs.
 Location 0xc8004008 (GPINR) is set to 0x0000affd (0b1010 1111 1111 1101), meaning GPIO[14,12,1] are reading as 0, and the rest are reading as 1.
 Location 0xc800400c (GPISR) is set to 0x0000a0d3 (0b1010 0000 1101 0011), meaning there are interrupts pending on GPIO[7,6,4,1,0].
 Location 0xc8004010 (GPIT1R) is set to 0x00009248 (0b0000 0000 0000 0000 1001 0010 0100 1000), meaning GPIO[7,6,0] are active high interrupts, and GPIO[5:1] are active low interrupts.
 Location 0xc8004014 (GPIT2R) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.
 Location 0xc8004018 (GPCLKR) is set to 0x017f01ff (0b0000 0001 0111 1111 0000 0001 1111 1111), meaning GPIO[15:14] are clock outputs.
to:

Location 0xc8004000 (GPOUTR) is set to 0x000020C0 (0b0010 0000 1100 0000), meaning GPIO[13,7,6] are set to 1.

Location 0xc8004004 (GPOER) is set to 0x00001F3F (0b0001 1111 0011 1111), meaning GPIO[12:8] and GPIO[5:0] are inputs or tristated, and GPIO[15:13] and GPIO[7:6] are outputs.

Location 0xc8004008 (GPINR) is set to 0x0000affd (0b1010 1111 1111 1101), meaning GPIO[14,12,1] are reading as 0, and the rest are reading as 1.

Location 0xc800400c (GPISR) is set to 0x0000a0d3 (0b1010 0000 1101 0011), meaning there are interrupts pending on GPIO[7,6,4,1,0].

Location 0xc8004010 (GPIT1R) is set to 0x00009248 (0b0000 0000 0000 0000 1001 0010 0100 1000), meaning GPIO[7,6,0] are active high interrupts, and GPIO[5:1] are active low interrupts.

Location 0xc8004014 (GPIT2R) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.

Location 0xc8004018 (GPCLKR) is set to 0x017f01ff (0b0000 0001 0111 1111 0000 0001 1111 1111), meaning GPIO[15:14] are clock outputs.

Restore
November 10, 2005, at 02:46 PM by rwhitby --
Changed lines 31-43 from:

Location 0xc8004000 (GPOUTR) is set to 0x000020C0 (0b0010 0000 1100 0000), meaning GPIO[13,7,6] are set to 1.

Location 0xc8004004 (GPOER) is set to 0x00001F3F (0b0001 1111 0011 1111), meaning GPIO[12:8] and GPIO[5:0] are inputs or tristated, and GPIO[15:13] and GPIO[7:6] are outputs.

Location 0xc8004008 (GPINR) is set to 0x0000affd (0b1010 1111 1111 1101), meaning GPIO[14,12,1] are reading as 0, and the rest are reading as 1.

Location 0xc800400c (GPISR) is set to 0x0000a0d3 (0b1010 0000 1101 0011), meaning there are interrupts pending on GPIO[7,6,4,1,0].

Location 0xc8004010 (GPIT1R?) is set to 0x00009248 (0b0000 0000 0000 0000 1001 0010 0100 1000), meaning GPIO[7,6,0] are active high interrupts, and GPIO[5:1] are active low interrupts.

Location 0xc8004014 (GPIT2R?) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.

Location 0xc8004018 (GPCLKR) is set to 0x017f01ff (0b000 00001 0111 1111 0000 0001 1111 1111), meaning ...

to:
 Location 0xc8004000 (GPOUTR) is set to 0x000020C0 (0b0010 0000 1100 0000), meaning GPIO[13,7,6] are set to 1.

 Location 0xc8004004 (GPOER) is set to 0x00001F3F (0b0001 1111 0011 1111), meaning GPIO[12:8] and GPIO[5:0] are inputs or tristated, and GPIO[15:13] and GPIO[7:6] are outputs.
 Location 0xc8004008 (GPINR) is set to 0x0000affd (0b1010 1111 1111 1101), meaning GPIO[14,12,1] are reading as 0, and the rest are reading as 1.
 Location 0xc800400c (GPISR) is set to 0x0000a0d3 (0b1010 0000 1101 0011), meaning there are interrupts pending on GPIO[7,6,4,1,0].
 Location 0xc8004010 (GPIT1R) is set to 0x00009248 (0b0000 0000 0000 0000 1001 0010 0100 1000), meaning GPIO[7,6,0] are active high interrupts, and GPIO[5:1] are active low interrupts.
 Location 0xc8004014 (GPIT2R) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.
 Location 0xc8004018 (GPCLKR) is set to 0x017f01ff (0b0000 0001 0111 1111 0000 0001 1111 1111), meaning GPIO[15:14] are clock outputs.
Restore
November 10, 2005, at 02:42 PM by rwhitby --
Changed lines 31-32 from:

So 0x00001F3F is 0b0001111100111111, meaning GPIO[12:8] and GPIO[5:0] are inputs or tristated, and GPIO[15:13] and GPIO[7:6] are outputs. So 0x000020C0 is 0b0010000011000000, meaning GPIO13?, GPIO7? and GPIO6? are set to 1.

to:

Location 0xc8004000 (GPOUTR) is set to 0x000020C0 (0b0010 0000 1100 0000), meaning GPIO[13,7,6] are set to 1.

Location 0xc8004004 (GPOER) is set to 0x00001F3F (0b0001 1111 0011 1111), meaning GPIO[12:8] and GPIO[5:0] are inputs or tristated, and GPIO[15:13] and GPIO[7:6] are outputs.

Location 0xc8004008 (GPINR) is set to 0x0000affd (0b1010 1111 1111 1101), meaning GPIO[14,12,1] are reading as 0, and the rest are reading as 1.

Location 0xc800400c (GPISR) is set to 0x0000a0d3 (0b1010 0000 1101 0011), meaning there are interrupts pending on GPIO[7,6,4,1,0].

Location 0xc8004010 (GPIT1R?) is set to 0x00009248 (0b0000 0000 0000 0000 1001 0010 0100 1000), meaning GPIO[7,6,0] are active high interrupts, and GPIO[5:1] are active low interrupts.

Location 0xc8004014 (GPIT2R?) is set to 0x00000249 (0b0000 0000 0000 0000 0000 0010 0100 1001), meaning GPIO[11:8] are active high interrupts, and GPIO[12] is an active low interrupt.

Location 0xc8004018 (GPCLKR) is set to 0x017f01ff (0b000 00001 0111 1111 0000 0001 1111 1111), meaning ...

Restore
November 10, 2005, at 02:26 PM by rwhitby --
Changed line 9 from:
GPIO[4]AB26TBD  
to:
GPIO[4]AB26TBD Output
Changed lines 31-32 from:

So 0x0000200 is 0b0010000011000000, meaning GPIO13?, GPIO7? and GPIO6? are outputs.

to:

So 0x00001F3F is 0b0001111100111111, meaning GPIO[12:8] and GPIO[5:0] are inputs or tristated, and GPIO[15:13] and GPIO[7:6] are outputs. So 0x000020C0 is 0b0010000011000000, meaning GPIO13?, GPIO7? and GPIO6? are set to 1.

Restore
November 10, 2005, at 01:44 PM by rwhitby --
Added lines 23-31:

Here is the way to determine GPIO connections: 

 RedBoot> cache off
 RedBoot> x -b 0xc8004000
 C8004000: 00 00 20 C0 00 00 1F 3F  00 00 AF FD 00 00 A0 C3  |.. ....?........|
 C8004010: 00 00 92 48 00 00 02 49  01 7F 01 FF 00 00 00 00  |...H...I........|

So 0x0000200 is 0b0010000011000000, meaning GPIO13?, GPIO7? and GPIO6? are outputs.

Restore
November 10, 2005, at 01:33 PM by rwhitby --
Changed lines 1-10 from:

The IXP420 CPU has 16 General Purpose Input/Output (GPIO) pins which are used to interface to external hardware. In the case of the NSLU2, the GPIO pins are used to monitor the buttons, control the LEDs, connect to the RTC and USB 2.0 controller.

GPIO(8) should actually be assigned as INTD on the PCI bus but it's been set as an output instead of tristate. It is connected to the power circuitry and is used to power down the NSLU2.

GPIO(15) is GPIO_CLK1 and is running at 33MHz. It is required to access the Flash memory on the expansion bus. After power-up the IXP420 is configured to provide a clock on this GPIO pin. If the clock output on this pin is disabled, access to the Flash is impossible.

The USB 2.0 controller can be configured to only use INTA which would free up GPIO(9) and GPIO(10). If the USB 2.0 controller tristates the INTB0 and INTC0 pins when they are disabled then we may reuse the GPIOs without cutting traces. If the USB 2.0 controller however actively pulls the pin high or low even when disabled then we must cut traces to allow reuse of the GPIOs.

A much safer and easier option to add extra IO pins is to use a I²C IO extender. Please see PinoutOfI2CPort? for more details on the I²C connection.

to:

The IXP420 CPU has 16 General Purpose Input/Output (GPIO) pins which are used to interface to external hardware. In the case of the NSLU2, the GPIO pins are used to monitor the buttons, control the LEDs, connect to the RTC, IDE controller and USB 2.0 controller.

Changed lines 9-19 from:
GPIO[4]AB26BuzzerBuzzerOutput
GPIO[5]Y25Power Button (Pulse when state change)Power Button via flipflopInput
GPIO[6]V21I²C SCLXC1205 RTC - SCL - Pin 6Output
GPIO[7]AA26I²C SDAXC1205 RTC - SDA - Pin 5Tristate
GPIO[8]W23Power Off (1 = Turn Off)R10Output
GPIO[9]V22PCI INTCuPD720101 USB (EHCI) - INTC0 - Pin 43Input
GPIO[10]Y26PCI INTBuPD720101 USB (OHCI #2) - INTB0 - Pin 88Input
GPIO[11]W25PCI INTAuPD720101 USB (OHCI #1) - INTA0 - Pin 125Input
GPIO[12]W26Reset Button (0 = Pressed)Reset ButtonInput
GPIO[13]V24PCI ResetuPD720101 USB - VBBRST0 - Pin 87Output
GPIO[14]U22PCI Clock (33MHz)uPD720101 USB - PCLK - Pin 42Output
to:
GPIO[4]AB26TBD  
GPIO[5]Y25I²C SDARTC - SDATristate
GPIO[6]V21I²C SCLRTC - SCLOutput
GPIO[7]AA26PCI INTA Input
GPIO[8]W23PCI INTB Input
GPIO[9]V22PCI INTC Input
GPIO[10]Y26PCI INTD Input
GPIO[11]W25PCI INTE Input
GPIO[12]W26Power Off (1 = Turn Off)TBDOutput
GPIO[13]V24PCI ResetTBDOutput
GPIO[14]U22PCI Clock (33MHz)TBDOutput
Added lines 21-22:
TBF Reset Button (0 = Pressed)Reset ButtonInput
TBF Power Button (Pulse when state change)Power Button via flipflopInput
Restore
November 10, 2005, at 01:19 PM by rwhitby --
Added lines 1-28:

The IXP420 CPU has 16 General Purpose Input/Output (GPIO) pins which are used to interface to external hardware. In the case of the NSLU2, the GPIO pins are used to monitor the buttons, control the LEDs, connect to the RTC and USB 2.0 controller.

GPIO(8) should actually be assigned as INTD on the PCI bus but it's been set as an output instead of tristate. It is connected to the power circuitry and is used to power down the NSLU2.

GPIO(15) is GPIO_CLK1 and is running at 33MHz. It is required to access the Flash memory on the expansion bus. After power-up the IXP420 is configured to provide a clock on this GPIO pin. If the clock output on this pin is disabled, access to the Flash is impossible.

The USB 2.0 controller can be configured to only use INTA which would free up GPIO(9) and GPIO(10). If the USB 2.0 controller tristates the INTB0 and INTC0 pins when they are disabled then we may reuse the GPIOs without cutting traces. If the USB 2.0 controller however actively pulls the pin high or low even when disabled then we must cut traces to allow reuse of the GPIOs.

A much safer and easier option to add extra IO pins is to use a I²C IO extender. Please see PinoutOfI2CPort? for more details on the I²C connection.

GPIOIXP BallFunctionConnected to:Configured as:
GPIO[0]Y22Red Status LED (1 = On)Status LEDOutput
GPIO[1]W21Green Ready LED (1 = On)Ready LEDOutput
GPIO[2]AC26Disk 2 LED (0 = On)Disk 2 LEDOutput
GPIO[3]AA24Disk 1 LED (0 = On)Disk 1 LEDOutput
GPIO[4]AB26BuzzerBuzzerOutput
GPIO[5]Y25Power Button (Pulse when state change)Power Button via flipflopInput
GPIO[6]V21I²C SCLXC1205 RTC - SCL - Pin 6Output
GPIO[7]AA26I²C SDAXC1205 RTC - SDA - Pin 5Tristate
GPIO[8]W23Power Off (1 = Turn Off)R10Output
GPIO[9]V22PCI INTCuPD720101 USB (EHCI) - INTC0 - Pin 43Input
GPIO[10]Y26PCI INTBuPD720101 USB (OHCI #2) - INTB0 - Pin 88Input
GPIO[11]W25PCI INTAuPD720101 USB (OHCI #1) - INTA0 - Pin 125Input
GPIO[12]W26Reset Button (0 = Pressed)Reset ButtonInput
GPIO[13]V24PCI ResetuPD720101 USB - VBBRST0 - Pin 87Output
GPIO[14]U22PCI Clock (33MHz)uPD720101 USB - PCLK - Pin 42Output
GPIO[15]U25Expansion Bus Clock (33MHz)IXP420 - EX_CLK - Ball M32Output
Restore
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Originally by rwhitby.
Page last modified on November 13, 2005, at 05:14 AM