NSLU2-Linux
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Info.MemoryMap History

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April 15, 2007, at 06:41 AM by Rob Lockhart -- added note about 256MiB
Added line 26:

Note also that default NSLU2 comes with 32MiB even though the range above for memory implies 256MiB space.

October 10, 2004, at 01:01 AM by tman --
Changed lines 5-7 from:
0x00000000256SDRAM (cached) ***
0x10000000256SDRAM (alias)
0x20000000256SDRAM (uncached)
to:
0x0000000032SDRAM (cached) ***
0x1000000032SDRAM (alias)
0x2000000032SDRAM (uncached)
Added line 17:
Changed lines 22-25 from:
  1. When the configuration register is set to logic 0 the SDRAM occupies the lowest 256 MB of address.

see page 205 of the intel developer's manual for the MUCH more detailed version. :)

to:
  1. When the configuration register is set to logic 0, the SDRAM occupies the lowest 256 MB of address.
Changed line 24 from:

and, of course, the NSLU2 only has 32MB of RAM. :)

to:

see page 205 of the Intel developer's manual for the MUCH more detailed version. :)

September 13, 2004, at 05:19 AM by ka6sox --
Changed line 1 from:

this is taken out of the RedBoot code, and is more or less correct:

to:

This is taken out of the RedBoot code, and is more or less correct:

Changed lines 3-15 from:

Physical Address Size (MB) Description


0x00000000 256 SDRAM (cached) ***
0x10000000 256 SDRAM (alias)
0x20000000 256 SDRAM (uncached)
:0x48000000 64 PCI Data
:0x50000000 16 Flash (CS0)
:0x51000000 112 CS1 - CS7
:0x60000000 64 Queue Manager
:0xC0000000 1 PCI Controller
:0xC4000000 1 Exp. Bus Config
:0xC8000000 1 Misc IXP425 IO
:0xCC000000 1 SDRAM Config

to:
Physical AddressSize (MB)Description
0x00000000256SDRAM (cached) ***
0x10000000256SDRAM (alias)
0x20000000256SDRAM (uncached)
0x4800000064PCI Data
0x5000000016Flash (CS0)
0x51000000112CS1 - CS7
0x6000000064Queue Manager
0xC00000001PCI Controller
0xC40000001Exp. Bus Config
0xC80000001Misc IXP425 IO
0xCC0000001SDRAM Config
September 13, 2004, at 05:05 AM by ka6sox --
Changed line 1 from:

this is taken out of the RedBoot code, and is more or less correct:

to:

this is taken out of the RedBoot code, and is more or less correct:

September 13, 2004, at 05:04 AM by ka6sox --
Changed lines 9-10 from:
0x50000000 16 Flash (CS0?)
0x51000000 112 CS1? - CS7?\\
to:
0x50000000 16 Flash (CS0)
0x51000000 112 CS1 - CS7\\
Changed line 14 from:

:0xC8000000 1 Misc IXP425 IO\\

to:

:0xC8000000 1 Misc IXP425 IO\\

Changed lines 19-22 from:

-When the configuration register is set to logic 1, the Expansion Bus occupies the lowest 256 MB of address space. -When the configuration register is set to logic 0 the SDRAM occupies the lowest 256 MB of address.

to:
  1. When the configuration register is set to logic 1, the Expansion Bus occupies the lowest 256 MB of address space.
  2. When the configuration register is set to logic 0 the SDRAM occupies the lowest 256 MB of address.
Changed line 28 from:

[http://groups.yahoo.com/group/nslu2-linux/message/1303]

to:

[http://groups.yahoo.com/group/nslu2-linux/message/1303]

September 13, 2004, at 04:57 AM by ka6sox --
Changed lines 27-29 from:

and, of course, the NSLU2 only has 32MB of RAM. :)

to:

and, of course, the NSLU2 only has 32MB of RAM. :)

[http://groups.yahoo.com/group/nslu2-linux/message/1303]

September 13, 2004, at 04:56 AM by ka6sox --
Changed lines 4-15 from:

--------- -----------

0x00000000 256 SDRAM (cached) **** 0x10000000 256 SDRAM (alias) 0x20000000 256 SDRAM (uncached) 0x48000000 64 PCI Data 0x50000000 16 Flash (CS0?) 0x51000000 112 CS1? - CS7? 0x60000000 64 Queue Manager 0xC0000000 1 PCI Controller 0xC4000000 1 Exp. Bus Config 0xC8000000 1 Misc IXP425 IO 0xCC000000 1 SDRAM Config

to:

0x00000000 256 SDRAM (cached) ***
0x10000000 256 SDRAM (alias)
0x20000000 256 SDRAM (uncached)
:0x48000000 64 PCI Data
:0x50000000 16 Flash (CS0?)
:0x51000000 112 CS1? - CS7?
:0x60000000 64 Queue Manager
:0xC0000000 1 PCI Controller
:0xC4000000 1 Exp. Bus Config
:0xC8000000 1 Misc IXP425 IO
:0xCC000000 1 SDRAM Config

Changed line 17 from:
  • The lowest 256MB of address space is configurable based on the value
to:

***The lowest 256MB of address space is configurable based on the value

Changed lines 27-29 from:

and, of course, the NSLU2 only has 32MB of RAM. :)

to:

and, of course, the NSLU2 only has 32MB of RAM. :)

September 13, 2004, at 04:39 AM by ka6sox --
Changed lines 1-29 from:

Describe MemoryMap here.

to:

this is taken out of the RedBoot code, and is more or less correct:

Physical Address Size (MB) Description


--------- -----------

0x00000000 256 SDRAM (cached) **** 0x10000000 256 SDRAM (alias) 0x20000000 256 SDRAM (uncached) 0x48000000 64 PCI Data 0x50000000 16 Flash (CS0?) 0x51000000 112 CS1? - CS7? 0x60000000 64 Queue Manager 0xC0000000 1 PCI Controller 0xC4000000 1 Exp. Bus Config 0xC8000000 1 Misc IXP425 IO 0xCC000000 1 SDRAM Config

  • The lowest 256MB of address space is configurable based on the value

of a configuration register located in the Expansion Bus Controller: -When the configuration register is set to logic 1, the Expansion Bus occupies the lowest 256 MB of address space. -When the configuration register is set to logic 0 the SDRAM occupies the lowest 256 MB of address.

see page 205 of the intel developer's manual for the MUCH more detailed version. :)

and, of course, the NSLU2 only has 32MB of RAM. :)

view · edit · print · history · Last edited by Rob Lockhart.
Based on work by tman and ka6sox.
Originally by ka6sox.
Page last modified on April 15, 2007, at 06:41 AM