NSLU2-Linux
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December 27, 2009, at 10:44 PM by anywhere -- every pci bus ball is routed physically (hand-soldering) accessible outside the ixp420 on nslu2-pcb...
Changed lines 10-11 from:

The PCI bus is used to connect the NEC USB chip to the IXP420 and it is not possible to connect anything else as the required lines are also not brought out. Removal of the NEC USB chip to gain access to the PCI signals is the only way.

to:

The PCI bus is used to connect the NEC USB chip to the IXP420 and it is possible to connect any 33MHz PCI device to it, the required lines are even brought out of the BGA-chip. Since one 33MHZ deivice is enough to slow down every 66MHZ device to 33MHz, removal of the NEC USB chip is only necessary to run a 66MHz PCI bus.

until yet It has not been verified whetever any nslu2 firmware kernel supports irq sharing needed to run more than one pci device on the isp420, nor whetever any firmware's kernel scans the bus for devices and whetever they exclude/disregard recognized devices when mapping pci device addresses to the memory address space.

May 18, 2007, at 05:16 PM by BrianZhou -- link to wikipedia XScale
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The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and is rated for 266MHz operation. Units supplied by Linksys, before May 2006 run at 133 Mhz and can set for 266MHz operation using a simple modification. After this manufacture date, most users have discovered their Nslu2 already operating at 266MHz.

to:

The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and is rated for 266MHz operation. Units supplied by Linksys, before May 2006 run at 133 Mhz and can set for 266MHz operation using a simple modification. After this manufacture date, most users have discovered their Nslu2 already operating at 266MHz.

Changed lines 12-13 from:

The expansion bus is used to connect the flash chip. It has not been verified whether the other expansion bus enables have been brought out. The expansion bus is also used for configuration of the XScale core.

to:

The expansion bus is used to connect the flash chip. It has not been verified whether the other expansion bus enables have been brought out. The expansion bus is also used for configuration of the XScale core.

May 11, 2007, at 08:50 PM by xkr47 -- added note that the cpu supports little endian as well
Changed lines 2-3 from:

Due to limitations of the IXP NPE access library and microcode at the time of release, the NSLU2 runs in big endian mode.

to:

Due to limitations of the IXP NPE access library and microcode at the time of release, the NSLU2 runs in big endian mode (the cpu supports little endian as well).

February 13, 2007, at 01:13 PM by carrick --
Changed lines 1-2 from:

The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and is rated for 266MHz operation. As supplied by Linksys, it runs at 133 Mhz and can set for 266MHz operation using a simple modification. Due to limitations of the IXP NPE access library and microcode at the time of release, the NSLU2 runs in big endian mode.

to:

The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and is rated for 266MHz operation. Units supplied by Linksys, before May 2006 run at 133 Mhz and can set for 266MHz operation using a simple modification. After this manufacture date, most users have discovered their Nslu2 already operating at 266MHz. Due to limitations of the IXP NPE access library and microcode at the time of release, the NSLU2 runs in big endian mode.

July 17, 2005, at 02:32 PM by tman --
Changed lines 1-2 from:

The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

to:

The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and is rated for 266MHz operation. As supplied by Linksys, it runs at 133 Mhz and can set for 266MHz operation using a simple modification. Due to limitations of the IXP NPE access library and microcode at the time of release, the NSLU2 runs in big endian mode.

Changed lines 7-8 from:

The IXP420 has two serial ports, one is used for the serial console on J2 and the other is a receive only port as it is partially connected. Please see PinoutOfInternalSerialPort for more details.

to:

The IXP420 has two serial ports, one is used for the serial console on J2 and the other is a receive only port as it is partially connected. Please see PinoutOfInternalSerialPort for more details.

Changed lines 11-20 from:

The expansion bus is used to connect the flash chip. It has not been verified whether the other expansion bus enables have been brought out.

The JTAG port is connected to several unpopulated resistor pads on the reverse of the PCB. Please see PinoutOfJTAGPort for more details.

The IXP420 GPIO pins are all used for various functions and are not available.

The IXP42X? product line features a IXP400 Digital Signal Processor and there is a Software Library from Intel for it. This library is a "software module that provides the basic voice and signal-processing functionalities for voice-over-Internet-protocols (VoIP?) applications..." It can do a-law or -law compression and decompression, high-pass filter, echo cancellation as explained in the Api Reference Manual. You can also read the Programmer's Guide.

to:

The expansion bus is used to connect the flash chip. It has not been verified whether the other expansion bus enables have been brought out. The expansion bus is also used for configuration of the XScale core.

The JTAG port is connected to several unpopulated resistor pads on the reverse of the PCB. Please see PinoutOfJTAGPort for more details.

The IXP420 GPIO pins are all used for various functions and are not available.

The IXP420 has some DSP features like a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data. These can be accessed using a software library from Intel. The library is a "software module that provides the basic voice and signal-processing functionalities for voice-over-Internet-protocols (VoIP) applications..." It provides functions for a-law and μ-law compression/decompression, high pass filters and echo cancellation as explained in the API Reference Manual and the Programmer's Guide.

July 16, 2005, at 06:13 PM by Anonymous -- some informations about the dsp
Changed lines 17-20 from:

The IXP42X? product line features a IXP400 Digital Sginal Processor and there is a Software Library from Intel for it. This library is a "software module that provides the basic voice and signal-processing functionalities for voice-over-Internet-protocols (VoIP?) applications..." It can do a-law or -law compression and decompression, high-pass filter, echo cancellation as explained in the Api Reference Manual. You can also read the |Programmer's Guide.

to:

The IXP42X? product line features a IXP400 Digital Signal Processor and there is a Software Library from Intel for it. This library is a "software module that provides the basic voice and signal-processing functionalities for voice-over-Internet-protocols (VoIP?) applications..." It can do a-law or -law compression and decompression, high-pass filter, echo cancellation as explained in the Api Reference Manual. You can also read the Programmer's Guide.

July 16, 2005, at 06:12 PM by A --
Added lines 16-20:

The IXP42X? product line features a IXP400 Digital Sginal Processor and there is a Software Library from Intel for it. This library is a "software module that provides the basic voice and signal-processing functionalities for voice-over-Internet-protocols (VoIP?) applications..." It can do a-law or -law compression and decompression, high-pass filter, echo cancellation as explained in the Api Reference Manual. You can also read the |Programmer's Guide.

July 01, 2005, at 10:37 AM by tman --
Changed lines 1-2 from:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

to:

The NSLU2 has an Intel IXP420 as its processor. Currently NSLU2's are supplied with a B0 stepping IXP420. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

December 20, 2004, at 02:12 AM by tman --
Changed line 3 from:

The CPU is supported by 8MB of internal flash memory and 32MB of SDRAM.

to:

The CPU is connected to 8MB of flash memory and 32MB of SDRAM on the PCB.

December 16, 2004, at 04:32 AM by rwhitby --
Changed lines 1-3 from:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

to:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

The CPU is supported by 8MB of internal flash memory and 32MB of SDRAM.

November 23, 2004, at 02:57 PM by tman --
Changed line 1 from:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale? core inside the IXP420 is based on a ARMv5TE? architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

to:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale core inside the IXP420 is based on a ARMv5TE architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

November 23, 2004, at 03:56 AM by jkpeters_37 --
Changed line 1 from:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale? core inside the IXP420 is based on a ARMv5TE? architecture and is running in big endian mode.

to:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale? core inside the IXP420 is based on a ARMv5TE? architecture and runs at 266 Mhz in big endian mode. It also supports special DSP instructions with a MAC (multiply/accumulate) unit featuring a 40-bit accumulator and support for 16-bit packed data.

November 23, 2004, at 03:39 AM by jkpeters_37 --
Changed line 1 from:

The NSLU2 has an Intel IXP420 as it's processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale? core inside the IXP420 is based on a ARMv5TE? architecture and is running in big endian mode.

to:

The NSLU2 has an Intel IXP420 as its processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale? core inside the IXP420 is based on a ARMv5TE? architecture and is running in big endian mode.

November 07, 2004, at 04:12 AM by tman --
Changed line 1 from:

The NSLU2 has an Intel IXP420 as it's processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces.

to:

The NSLU2 has an Intel IXP420 as it's processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces. The XScale? core inside the IXP420 is based on a ARMv5TE? architecture and is running in big endian mode.

Changed lines 13-15 from:

The IXP420 GPIO pins are all used for various functions and are not available.

Note that the architecture is neither ARM nor ARMv4L, it is ARMv5TE.

to:

The IXP420 GPIO pins are all used for GPIOConnections various functions? and are not available.

October 31, 2004, at 12:26 AM by tman --
Changed line 13 from:

The IXP420 GPIO pins are all used for various functions and are not available. The possible exception is GPIO 8 which does not seem to have a purpose. It has not been traced out on the PCB yet so there may be a usage for it. See GPIOConnections for more details.

to:

The IXP420 GPIO pins are all used for various functions and are not available.

October 10, 2004, at 02:21 PM by tman --
Changed line 15 from:

Note that the architecture is neither ARM nor ARMv4L?, it is ARMv5TE?.

to:

Note that the architecture is neither ARM nor ARMv4L, it is ARMv5TE.

October 10, 2004, at 02:18 PM by tman --
Changed line 15 from:

Note that the architecture is neither arm nor armv4l, it is armv5te.

to:

Note that the architecture is neither ARM nor ARMv4L?, it is ARMv5TE?.

October 10, 2004, at 01:39 PM by kolla --
Changed lines 13-15 from:

The IXP420 GPIO pins are all used for various functions and are not available. The possible exception is GPIO 8 which does not seem to have a purpose. It has not been traced out on the PCB yet so there may be a usage for it. See GPIOConnections for more details.

to:

The IXP420 GPIO pins are all used for various functions and are not available. The possible exception is GPIO 8 which does not seem to have a purpose. It has not been traced out on the PCB yet so there may be a usage for it. See GPIOConnections for more details.

Note that the architecture is neither arm nor armv4l, it is armv5te.

October 10, 2004, at 12:57 AM by tman --
Changed lines 1-13 from:

Describe CPUOverview here.

to:

The NSLU2 has an Intel IXP420 as it's processor. This is a stripped down version of the IXP425 and therefore does not have any of the cryptographic features or extra interfaces.

There are two MII interfaces of which only one is wired to an Ethernet PHY. The other MII interface is not accessible at all as the designers of the PCB did not bring the necessary BGA ball connections out.

The IXP420 has two serial ports, one is used for the serial console on J2 and the other is a receive only port as it is partially connected. Please see PinoutOfInternalSerialPort for more details.

The PCI bus is used to connect the NEC USB chip to the IXP420 and it is not possible to connect anything else as the required lines are also not brought out. Removal of the NEC USB chip to gain access to the PCI signals is the only way.

The expansion bus is used to connect the flash chip. It has not been verified whether the other expansion bus enables have been brought out.

The JTAG port is connected to several unpopulated resistor pads on the reverse of the PCB. Please see PinoutOfJTAGPort for more details.

The IXP420 GPIO pins are all used for various functions and are not available. The possible exception is GPIO 8 which does not seem to have a purpose. It has not been traced out on the PCB yet so there may be a usage for it. See GPIOConnections for more details.

view · edit · print · history · Last edited by anywhere.
Based on work by BrianZhou, xkr47, carrick, tman, Anonymous, A, rwhitby, jkpeters_37, and kolla.
Originally by tman.
Page last modified on December 27, 2009, at 10:44 PM